As the device size shrinks, especially into the deep-submicron regime, and clock frequency increases, the electrical properties of circuit design features become more prominent, and chips are more susceptive to breakdown during fabrication due to, for example, antenna effect or to wear out over time due to, for example, electro-migration.
One approach assumes the thickness of certain features, such as the features or interconnects, to be a certain numeric value and manipulates the widths and/or lengths of such features to achieve the design objectives. Another approach obtains the thickness of the features from process model and/or fabrication information and use such information together with the width and/or length information to more accurately estimate the bulk properties of such features. Both approaches exist for practical purposes as the IC designs today or in the near future are not all that sensitive to variations due to the deviations of these features from their true profiles.
Moreover, the continual effort to scale down to the deep submicron region and/or to increase clock frequency requires multilevel interconnection architecture to minimize the timing delay due to parasitic resistance and capacitance. As the devices shrinks smaller, the delay caused by the increased R-C time constant becomes more significant over the delay caused by the actual profiles of the features. In order to reduce the R-C time constant, interconnect materials with lower resistivity and interlayer films with lower capacitance are required. However, the use of low-k dielectric material aggravates the electro-migration problem due to the poor thermal conductivity of these low-k dielectric materials.
One way of resolving the aforementioned problems introduced by the continual reduction in feature sizes is to impose certain density rules for metal filling. Such rules typically comprise certain maximum and minimum densities within certain windows on the chip. Some other rules impose different density limits among different window areas. However, such rules typically assume that the thickness of the wire is constant according to certain formulae and therefore manipulate only the width or spacing of the wires to achieve the design goals. As a result, such rules typically assume the cross-sectional profile of a wire to be rectangular. More advanced rules may compute results in terms of an equivalent rectangular cross section, allowing some compensation for non-rectangular cross sections. However, even these more advanced approaches only consider the wire properties as a function of a few characteristics, such as the width of a wire and the distance to the nearest neighbors. Although these assumptions arose out of practical considerations and have worked while the thickness variation is relatively insignificant as compared to the geometry sizes, such an assumption appears to be outdated, especially in light of the current development in incorporating the topological variations of each film into the electronic designs and the continuously shrinkage in sizes of device features. Moreover, wire width cannot be arbitrarily changed due to the polycrystalline structure of the interconnect materials. As a result, additional methods have been developed to slot certain wires such that the metal density within certain region falls within the prescribed maximum and minimum limits.
Nonetheless, the above rule-based methods pose new problems. For instance, a good interconnect may be wrongfully determined to be improper for failing to meet certain design rules or for producing unacceptable R-C delay even though the interconnect actually satisfies the design goals by having certain thickness that is different from the assumed value. A contrary example is that a bad interconnect may also be wrongfully determined to be proper for meeting the metal density rules and/or the delay requirement.
Additionally, the continual effort to scale down to the deep submicron region renders the design more susceptible to even slight variations of or deviations of the design features from their true profile particularly in deep submicron designs. Furthermore, using presumed thicknesses of certain features or thickness information from the process/fabrication models without truthfully approximating the true profiles of certain features would sometimes falsely identify a perfectly good design to be bad and a bad design to be good. In some other times, using presumed thicknesses or cross sections of certain features or thickness information from the process/fabrication models without truthfully approximating the true profiles of certain features would falsely report that certain designs fail to meet certain objectives and cause unnecessary redesign or waste of valuable real estate in the chip area.